In conventional scan techniques, including LSSD, the sequential portions of a circuit, such as latches or flip-flops, are serially connected through switching circuits to form a shift register. During normal operation, the switches are open. When it is desired to test the circuit, the switches are closed and predetermined test data is propagated into the resulting shift register until the shift register is fully loaded. The switches are then reopened and the sequential circuits are returned to normal operation while a predetermined logic operation is performed. Finally, the switches are again closed in order to clock out of the shift register the result of the logic operation for comparison with the result expected.
Clocks for scan circuits have been provided in a number of ways, as disclosed by E. J. McCluskey, "A survey of Design for Testability Techniques" VLSI Design, December 1984. One clocking technique disclosed by the McCluskey article, provides a completely independent set of clocks just for scan which must be routed, along with the functional clocks, to every latch. With this technique the sets of functional clocks and scan clocks are toggled on and off at the chip level in order to execute the scan cycle. In order to maintain proper timing relationships these clocks must all be balanced individually and against each other, leading to increased complexity of the circuit. Typically, scan testing cannot be performed at system speeds because of this complexity.
Another technique, as disclosed in U.S. Pat. No. 4,961,013, entitled "Apparatus for Generation of Scan Control Signals for Initialization and Diagnosis of Circuitry in a Computer", to Obermeyer et al, employs a single set of clocks, but requires a multiplexer at the input of each latch or flip-flop to select, in accordance with a control signal, whether scan data or functional data is being input to the sequential circuit. However, Obermeyer requires the multiplexer control signal to be distributed to every latch, and the multiplexers add delay to the functional data path as well as require additional circuit area.
U.S. Pat. No. 5,220,217, entitled "Circuit for the Generation of a Scanning Clock in an Operational Analysis Device of the Serial Type for an Integrated Circuit", by Scarra et al, discloses a clock generator which produces a machine clock and a scanning .clock from a system clock. Scarra's machine clock is normally coincident with the system clock. When a scanning clock is needed, Scarra clamps the machine clock and enables a scanning clock in response to a control signal. The state in which the machine clock is clamped determines whether the scanning clock inverts or passes the system clock.
The dependent relationship between Scarra's machine clock and scanning clock limits its ability to test certain sequential circuits. Scarra teaches a circuit capable of producing scan and functional clocks for testing a master-slave register having an output that changes on the low phase of the system clock, but would require modification to produce scan and functional clocks for testing a master-slave register having an output that changes on the high phase of the system clock. Scarra's circuit could not be used to test a register file.
Prior art techniques force the circuit designer to balance undesired tradeoffs against each other. One tradeoff is less than complete test coverage, which increases the risk that a defective chip will test good. Another tradeoff is limiting the variety of sequential circuits used in the chip to those that can be tested by prior art schemes, which may increase cost and decrease circuit speed. Equally undesired for its increase in cost and area and decrease in speed is adding compensating logic to the sequential circuits.
Additionally, some of the prior art may not comply with a standard for boundary scan testing established by the Institute of Electrical and Electronic Engineers (IEEE) and known as Joint Test Action Group (JTAG) 1149.1.